MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 424

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
18.8.8.3 Stop Mode
18.9 Reset
18.10 Interrupts
18.10.1 Mode Fault (MODF) Flag
18.10.2 SPI Interrupt Flag (SPIF)
Advance Information
424
SPI operation in stop mode is the same as in doze mode with the
SPISDOZ bit set.
Reset initializes the SPI registers to a known startup state as described
in
reset and before writing to the SPIDR register is either indeterminate or
the byte last received from the master before the reset. Reading the
SPIDR after reset returns 0s.
MODF is set when the SS pin of a master SPI is driven low and the SS
pin is configured as a mode-fault input. If the SPIE bit is also set, MODF
generates an interrupt request. A mode fault clears the SPE, MSTR, and
DDRSP[2:0] bits. Clear MODF by reading SPISR with MODF set and
then writing to SPICR1. Reset clears MODF.
SPIF is set after the eighth SCK cycle in a transmission when received
data transfers from the shift register to SPIDR. If the SPIE bit is also set,
SPIF generates an interrupt request. Once SPIF is set, no new data can
be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading
SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.
Mode fault
Transmission complete
18.7 Memory Map and
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
Interrupt Request
Go to: www.freescale.com
Table 18-8. SPI Interrupt Request Sources
Registers. A transmission from a slave after
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MODF
SPIF
Flag
Enable Bit
SPIE
MOTOROLA