MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 503

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.10.8 QADC Clock (QCLK) Generation
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
QUEUE 1 AND QUEUE 2 TIMER
MODE RATE SELECTION
SYSTEM CLOCK
INPUT SAMPLE TIME
FROM CCW
Figure 19-42. QADC Clock Subsystem Functions
overrun. As with all continuous-scan queue operating modes, software
action is not needed between trigger events. Because both queues may
be triggered by the periodic/interval timer, see
Timer
Figure 19-42
provides the timing for the A/D converter state machine which controls
the timing of the conversion. The QCLK is also the input to a 17-stage
binary divider which implements the periodic/interval timer. To retain the
specified analog conversion accuracy, the QCLK frequency (f
must be within the tolerance specified in
Specifications
Before using the QADC, the prescaler must be initialized with values that
put the QCLK within the specified range. Though most applications
initialize the prescaler once and do not change it, write operations to the
prescaler fields are permitted.
2
Freescale Semiconductor, Inc.
8
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
for a summary of periodic/interval timer reset conditions.
2
7
PRESCALER
2
QPR[6:0]
8
PERIODIC TIMER/INTERVAL TIMER
Go to: www.freescale.com
2
is a block diagram of the clock subsystem. The QCLK
9
(Operating).
2
BINARY COUNTER
10
ATD CONVERTER
STATE MACHINE
2
11
SELECT
2
12
2
13
2
14
2
15
2
16
Queued Analog-to-Digital Converter (QADC)
2
17
Table 23-8. QADC Conversion
2
PERIODIC/INTERVAL TRIGGER
19.10.9 Periodic/Interval
SAR CONTROL
EVENT FOR Q1 AND Q2
SAR
10
Advance Information
Digital Control
QCLK
)
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