MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 423

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.8.8 Low-Power Mode Options
18.8.8.1 Run Mode
18.8.8.2 Doze Mode
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
A mode fault clears the SPE and MSTR bits and the DDRSP bits of the
SCK, MISO, and MOSI (or MOMI) pins. This forces those pins to be
high-impedance inputs to avoid any conflict with another output driver.
If the mode fault error occurs in bidirectional mode, the DDRSP bit of the
SISO pin is not affected, since it is a general-purpose I/O pin.
This subsection describes the low-power mode options.
Clearing the SPE bit in SPICR1 puts the SPI in a disabled, low-power
state. SPI registers are accessible, but SPI clocks are disabled.
SPI operation in doze mode depends on the state of the SPISDOZ bit in
SPICR2.
Although the slave shift register can receive MOSI data, it cannot
transfer data to SPIDR or set the SPIF flag in doze or stop mode. If the
slave enters doze mode in an idle state and exits doze mode in an idle
state, SPIF remains clear and no transfer to SPIDR occurs.
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If SPISDOZ is clear, the SPI operates normally in doze mode.
If SPISDOZ is set, the SPI clock stops, and the SPI enters a
low-power state in doze mode.
– Any master transmission in progress stops at doze mode entry
– Any slave transmission in progress continues if a master
Serial Peripheral Interface Module (SPI)
and resumes at doze mode exit.
continues to drive the slave SCK pin. The slave stays
synchronized to the master SCK clock.
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Serial Peripheral Interface Module (SPI)
Functional Description
Advance Information
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