MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 619

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
CLKOUT period jitter
10. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over 2 ms interval)
1. When the MFD in the PLL is set to 000, the minimum crystal reference frequency is 3 MHz.
2. All internal registers retain data at 0 Hz.
3. “Loss of reference frequency” is the reference frequency detected internally, which transitions the PLL into self-clocked
4. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
5. This parameter is characterized before qualification rather than 100% tested.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
8. Assuming a reference is available at powerup, lock time is measured from the time V
9. PLL is operating in 1:1 PLL mode.
mode.
default MFD/RFD settings.
synthesizer control register (SYNCR).
negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to
the PLL lock time to determine the total start-up time.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
for a given interval.
(4), (5), (7), (10)
Table 23-5. PLL Electrical Specifications (Continued)
Characteristic
(V
Freescale Semiconductor, Inc.
DD
For More Information On This Product,
measured at f
= 2.7 to 3.6 V, V
DD
and V
Preliminary Electrical Specifications
Go to: www.freescale.com
SS
and variation in crystal oscillator frequency increase the C
sys
max
SS
= 0 V, T
Symbol
C
Jitter
A
= T
L
to T
Preliminary Electrical Specifications
DD
H
Min
—
—
)
and V
PLL Electrical Specifications
DD
are valid to RSTOUT
Advance Information
Max
0.01
5
Jitter
percentage
LOR
% f
sys
Unit
sys
.
with
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