MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 119

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5.9 Debug and Emulation Support Signals
3.5.9.1 Test Reset (TRST)
3.5.9.2 Test Clock (TCLK)
3.5.9.3 Test Mode Select (TMS)
3.5.9.4 Test Data Input (TDI)
3.5.9.5 Test Data Output (TDO)
3.5.9.6 Debug Event (DE)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
These signals are used as the interface to the on-chip JTAG (Joint Test
Action Group) controller and also to interface to the OnCE logic.
This active-low input signal is used to initialize the JTAG and OnCE logic
asynchronously.
This input signal is the test clock used to synchronize the JTAG and
OnCE logic.
This input signal is used to sequence the JTAG state machine. TMS is
sampled on the rising edge of TCLK.
This input signal is the serial input for test instructions and data. TDI is
sampled on the rising edge of TCLK.
This output signal is the serial output for test instructions and data. TDO
is three-stateable and is actively driven in the shift-IR and shift-DR
controller states. TDO changes on the falling edge of TCLK.
This is a bidirectional, active-low signal. As an output, this signal will be
asserted for three system clocks, synchronous to the rising CLKOUT
edge, to acknowledge that the CPU has entered debug mode as a result
of a debug request or a breakpoint condition. As an input, this signal
provides multiple functions.
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Signal Description
Advance Information
Signal Descriptions
Signal Description
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