ml670100 Oki Semiconductor, ml670100 Datasheet - Page 100

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

7.2.3
7-8
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Timer Counter n (TMnC, n=0 - 5) is a 16-bit read/write register that increments with each
pulse from the count clock signal selected with the TMCLK field in Timer Control Register n
(TMnCON, n=0 - 5).Always use 16-bit access for this register. Reading or writing 8-bit data
produces unreliable operation.
After a system reset, this register contains 0x0000. Writing "1" to TMnEN, the bit with the
same number in the Timer Enable Register (TMEN), starts the counter. Writing "1" to
TMnDIS, the bit with the same number in the Timer Disable Register (TMDIS), stops the
counter.
Counter overflow generates an interrupt request (FTMOVn, n=0 - 5) and loads the contents of
Timer Register n (TMnR, n=0 - 5) into TMnC.
A write to TMnC automatically copies the same value to TMnR.
Bit Descriptions
CM/CAPEV
This flag indicates events as defined by the operating mode:
OVF
This flag indicates Timer Counter n (TMnC, n=0 - 5) overflow.
Counter overflow always sets it to "1" regardless of the timer channel's operating mode.
Timer Counters 0 to 5 (TMnC, n=0 - 5)
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- The auto-reload timer (ART) and pulse width modulation (PWM) modes do not modify
- Compare out (CMO) mode sets it to "1" and generates an interrupt request (EVENTn,
- Capture (CAP) mode sets it to "1" and generates an interrupt request (EVENTn, n=0 - 5)
this flag.
n=0 - 5) when the contents of Timer Counter n (TMnC, n=0 - 5) match those of Timer
General-Purpose Register n (TMnGR, n=0 - 5).
when it receives an event from Timer Input n pin (TMIN[n], n=0 - 5).
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Figure 7.4 : Timer Counters 0 to 5 (TMnC, n=0 - 5)
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