ml670100 Oki Semiconductor, ml670100 Datasheet - Page 196

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.4.3
11-40
The CPU instruction set includes the data swap (SWP) instruction, which exchanges data
between a memory location and a general-purpose register inside the CPU. While this
instruction is executing, the CPU does not release the bus, and the controller ignores any bus
requests from external devices.
Table 11.5 : Pins in High-Impedance States when Bus Release
Granting an external device access to the external bus has the following effects on external
memory access and DRAM self-refresh settings.
Lock Operation
Always
XA15 - 1
nLB/XA0
XD7 - 0
nCS0
nRD
nWRE/nWRL
- External memory access stalls until the CPU regains bus access. When the external
- Writing "1" to the RSR bit in the Refresh Control Register (RFCON) while the external
device negates the nBREQ signal to return control to the CPU, access proceeds, and the
CPU resumes execution.
device is master does not activate the DRAM self-refresh mode because nRAS and nCAS
are among the pins that remain in high-impedance states. When the external device
negates the nBREQ signal to return control to the CPU, these pins return to their normal
configurations, and the controller asserts the strobe signals to activate the DRAM self-
refresh mode.
I/O port pins configured for secondary function
XA23 - 16
XD15 - 8
nCS1
nHB/nWRH
nRAS1
nWH/nCASH
nRAS0
nCAS/nCASL
nWL/nWE