ml670100 Oki Semiconductor, ml670100 Datasheet - Page 50

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

4.1
4.1.1
4-2
The interrupt controller manages interrupt requests from 9 external sources and 19 internal
ones and passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ)
exception requests. It supports eight interrupt levels for each source for use in priority control.
Figure 4.1 gives a block diagram for the interrupt controller, which includes the following
components:
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Overview
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Block Diagram
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Interrupt Number Register (INR), which holds the interrupt number for the interrupt
request with the highest priority
Current Interrupt Level Register (CILR), which holds interrupt level flags for the
interrupts currently being processed
External FIQ Control Register (EFIQCON), which controls processing of external fast
interrupt requests
External IRQ Control Register (EIRCON), which specifies the detection methods for
external interrupt requests
Interrupt Request Registers 0 to 3 (IRRn, n=0 - 3), which contain flags tracking pending
interrupt requests
Interrupt Level Control Registers 0 to 15 (ILCONn, n=0 - 15), which specify the interrupt
levels for individual interrupt sources
Interrupt request detection circuitry
Interrupt priority judgment circuitry
The interrupt controller supports 9 external interrupt sources connected to nEFIQ and
nEIR[7:0] pins and 19 internal interrupt sources, including the serial ports and the
Flexible Timer (FTM) channels.
The interrupt controller simplifies interrupt priority control with a choice of eight interrupt
levels for each source.
The interrupt controller assigns a unique interrupt number to each source to permit rapid
branching to the appropriate routine.
Interrupt Request Level Register (IRLR), which holds the interrupt level for the interrupt
request with the highest priority