ml670100 Oki Semiconductor, ml670100 Datasheet - Page 34

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

2.8
2.8.1
2.8.2
31
N
condition code flags
30
Z
29
The CPU contains a Current Program Status Register (CPSR), plus four Saved Program
The N, Z, C and V bits are the condition code flags. These may be changed as a result of
arithmetic and logical operations, and may be tested to determine whether an instruction should
be executed.
In ARM state, all instructions may be executed conditionally.
The bottom 8 bits of a PSR (incorporating I, F, T and M [4:0]) are known collectively as the
control bits. These will change when an exception arises. If the CPU is executing in a
privileged mode, they can also be manipulated by software.
The Program Status Registers
Status Registers (SPSRs) for use by exception handlers. These registers
The arrangement of bits is shown in Figure 2.5: Program status register format.
The condition code flags
In THUMB state, only the Branch instruction is capable of conditional execution.
The control bits
C
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operating mode
The T bit
Interrupt disable bits
28
V
27
-
Overflow
Carry/Borrow/Extend
Zero
Negative/Less Than
26
-
Figure 2.5 : Program status register format
25
-
(reserved)
24
-
This reflects the operating state. When this bit is set, the CPU is
executing in THUMB state, otherwise it is executing in ARM state.
Note that the software must never change the state of the TBIT in
the CPSR. If this happens, the CPU will enter an unpredictable state.
The I and F bits are interrupt disable bits. When set, these disable
the IRQ and FIQ interrupts respectively.
23
-
-
8
-
7
I
F
6
5
T
control bits
M4 M3 M2 M1 M0
4
3
Mode bits
State bit
FIQ disable
IRQ disable
2
1
2-8
0