ml670100 Oki Semiconductor, ml670100 Datasheet - Page 203

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ml670100

Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
11.6.3
Figure 11.38 shows a sample configuration with the external data bus width to memory bank 2
set to 16 bits for connecting a DRAM with a data width of 16 bits.
Because this LSI uses an early write cycle, ground the DRAM's nOE pin. Set the BWB2 bit in
the Bus Width Control Register (BWCON) to "1" to set the external data bus width to 16. This
example uses a DRAM with a data width of 16 bits and separate nLCAS and nUCAS pins, so
set the DBAS bit in the DRAM Bank Control Register 2 (DR2CON) to "0" to access the bank
with two Column Address Strobe (nCAS) signals.
Because the DRAM has a data width of 16 bits and 9 pins each for the row and column
addresses, set the Address Multiplexing (AMUX) field in DR2CON to 2'b01 to shift the row
address 9 bits.
Connecting DRAM
Figure 11.38 : Connecting External DRAM
nCASH
DBSEL
nRAS0
nCASL
XD15
nWE
XD0
XD1
XD7
XD8
XD9
XA1
XA2
XA3
XA8
XA9
VDD
A0
A1
A2
A7
A8
DQ1
DQ2
DQ8
DQ9
DQ10
DQ16
nRAS
nLCAS
nUCAS
nWE
64K X 16 DRAM
nOE
GND
11-47

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