ml670100 Oki Semiconductor, ml670100 Datasheet - Page 172

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.2.8
11-16
Figure 11.10 : DRAM Bank 2 and 3 Programmable Wait Control Registers (DWnCON, n=2,3)
The DRAM Bank n Programmable Wait Control Register (DWnCON, n=2,3) is an 8-bit
read/write register that specifies the number of wait cycles automatically added to the CAS
assertion time during access to DRAM bank n.
After a system reset, this register contains 0x03.
Bit Descriptions
CAWA
The CAS Access Wait Added (CAWA) field specifies the number of wait cycles automatically
added to the CAS assertion time during access to DRAM bank n. The range is from 0 (no wait
cycles added) to 3.
DRAM Bank 2 and 3 Programmable Wait Control Registers (DWnCON, n=2,3)
7
0
6
0
A "0” indicates a reserved bit. Always write "0” to it.
Writing "1” produces unreliable operation.
5
0
4
0
3
0
2
0
1
00 CAS access wait cycles added = 0 cycles
01 CAS access wait cycles added = 1 cycle
10 CAS access wait cycles added = 2 cycles
11 CAS access wait cycles added = 3 cycles
CAWA
0