ml670100 Oki Semiconductor, ml670100 Datasheet - Page 120

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

8.2.2
8.2.3
8-6
ASEVN
This bit specifies the parity logic (odd or even) for the parity bit, if present, for transmit and
receive operation. Setting it to "1" specifies even parity; writing "0," odd parity.
ASPEN
This bit enables/disables the parity bit for transmit and receive operation. Setting it to "1"
causes the interface to include the parity bit when transmitting and to check the parity when
receiving; writing "0" suppresses the parity bit.
ASLN
This bit controls the character length for transmit and receive operation. Setting it to "1" sets
the number of data bits to 7; writing "0," to 8.
The ASI Buffer Register (ASBUF) is an 8-bit read/write register that provides a common
interface to two buffers which hold transmitted and received data. Reading the register accesses
the receive buffer; writing to it accesses the transmit buffer.
When a receive operation terminates, the interface transfers the contents of the receive shift
register to the ASBUF receive buffer and generates a receive ready interrupt request (RVINT).
The buffer contents remain valid until the completion of the next receive operation.
For a transmit operation, the interface transfers the contents written to the ASBUF transmit
buffer to the transmit shift register and generates a transmit ready interrupt request (TRINT).
After a system reset, this register contains an indeterminate value.
The ASI shift registers are 8-bit registers that shift one bit at a time as the interface transfers
the data.
These registers are not accessible from programs.
ASI Buffer Register (ASBUF)
ASI Shift Registers
7
Figure 8.4 : ASI Buffer Register (ASBUF)
6
5
4
3
2
1
0