ml670100 Oki Semiconductor, ml670100 Datasheet - Page 30

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

2.7.1
In ARM state, 16 general registers and one or two status registers are visible at any one time. In
privileged (non-User) modes, mode-specific banked registers are switched in.
Register 15
Register 16
The ARM state register set
Figure 2.2 : Register organization in ARM state shows which registers are available in each
mode: the banked registers are marked with a shaded triangle.
The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these
except R15 are general-purpose, and may be used to hold either data or address values.
In addition to these, there is a seventeenth register used to store status information.
Register 14
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many
FIQ handlers do not need to save any registers. User, IRQ, Supervisor and Undefined each have
two banked registers mapped to R13 and R14, allowing each of these modes to have a private
stack pointer and link registers.
is used as the subroutine link register. This receives a copy of R15 when a
Branch and Link (BL) instruction is executed. At all other times it may be
treated as a general-purpose register. The corresponding banked registers
R14_svc, R14_irg, R14_fiq, and R14_und are similarly used to hold the
return values of R15 when interrupts and exceptions arise, or when Branch
and Link instructions are executed within interrupt or exception routines.
holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and
bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1]
contain the PC.
is the CPSR (Current Program Status Register). This contains condition code
flags and the current mode bits.
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