ml670100 Oki Semiconductor, ml670100 Datasheet - Page 180

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.2
11.3.2.1 Basic Access
11.3.2.2 Access with Wait Cycles
11-24
The external memory areas in the SRAM banks (0 and 1) are designed primarily for direct
connection to SRAM devices. Accessing them automatically generates the appropriate strobe
signals (nCS0, nCS1, nRD, nWRE/nWRL, nHB/nWRH, and nLB/XA0).
Basic access, access without wait cycles, to the SRAM banks (0 and 1) takes one clock cycle for
a read and two for a write.
Figure 11.17 shows the basic access timing for external memory areas in these two banks.
The two halves of the Programmable Wait Control Register (PWCON) specify the number of
programmable wait cycles automatically inserted for accesses to external memory areas in the
SRAM banks (0 and 1). The range is from 0 (no pausing) to 7.
The lowest two bits in the Wait Input Control Register (WICON) permit the use of nXWAIT
input to insert additional wait cycles for each bank. Sampling of nXWAIT input is at the rising
edges of the system clock (SYSCLK) signal. This input must therefore satisfy setup and hold
time conditions at these edges.
Figure 11.18 shows the access timing with two programmable wait cycles inserted; Figure
11.19, that with two programmable wait cycles inserted and the nXWAIT signal asserted.
Accessing External Memory in SRAM Banks (0 and 1)
Figure 11.17 : Basic External Access Timing for SRAM Banks (0 and 1)
SYSCLK
(CLKOUT)
nCS0
XA23 - XA0
nRD
XD15 - XD0
nWRH/nWRL
Read cycle
Read
Read
Write cycle
Write
Write