ml670100 Oki Semiconductor, ml670100 Datasheet - Page 87
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ml670100
Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
1.ML670100.pdf
(204 pages)
- Current page: 87 of 204
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6.3.2
The Watchdog Timer (WDT) is a 12-bit counter that counts pulses from an input clock in the
range 32TBCCLK to 256TBCCLK. Although it is possible to indirectly clear the contents to 0
by writing to the Watchdog Timer Control Register (WDTCON), the contents are otherwise
inaccessible to reads and writes.
After a system reset, the Watchdog Timer (WDT) is stopped.
In addition to the usual function of producing a system reset signal (WDTOV) upon counter
overflow, the Watchdog Timer (WDT) can also be configured as an interval timer.
In its watchdog timer configuration, writing 0x3C to WDTCON starts the WDT internal
counter and then alternately writing 0xC3 and 0x3C clears the WDT internal counter.
Not clearing the internal counter in time to prevent counter overflow generates a system reset
signal (WDTOV).
The Watchdog Timer (WDT) continues operating in HALT mode. To stop it, write "1" to the
ITM bit in the Time Base Generator Control Register (TBGCON) and "0" to the ITEN bit
before switching to HALT mode. These settings switch the timer to its interval timer
configuration and disable the internal counter. Writing "0" to the ITM bit switches the timer
back to its watchdog timer configuration and starts the internal counter counting from 0.
In its interval timer configuration, writing "1" to the ITM and ITEN bits in TBGCON enables
the interval timer and writing 0x3C to WDTCON then starts the WDT internal counter.
Subsequent writes of 0x3C to WDTCON reset the WDT internal counter to 0.
In its interval timer configuration, counter overflow does not generate a system reset signal
(WDTOV), but a Watchdog Timer (WDT) interrupt request signal (WDINT).
Figure 6.5 gives the basic structure of the Watchdog Timer (WDT).
Watchdog Timer (WDT)
Clock Input
(32TBCCLK to
256TBCCLK)
Reset
Figure 6.5 : Watchdog Timer (WDT) Structure
12-bit
Watchdog Timer (WDT)
Watchdog Timer
Control Register
(WDTCON)
Overflow
Alternately writing 0xC3 and 0x3C
clears the WDT internal counter
WDTOV
WDINT
6-7
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