ml670100 Oki Semiconductor, ml670100 Datasheet - Page 171

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.2.7
Figure 11.9 : DRAM Bank 2 and 3 Access Timing Control Registers (ATnCON, n=2,3)
BE
The Burst Enable (BE) bit specifies the access mode (random access or high-speed paged) for
bank n. Setting it to "1" specifies high-speed paged mode; resetting it to "0," random access
mode.
The DRAM Bank n Access Timing Control Register (ATnCON, n=2,3) is an 8-bit read/ write
register that specifies the RAS precharge time (t
delay between asserting the nRAS signal and asserting the nCAS signal, during access to
DRAM bank n.
After a system reset, this register contains 0x05.
Bit Descriptions
RP
The RAS Precharge (RP) bit specifies t
Setting it to "1" specifies two clock cycles; resetting it to "0," one.
RCD
The RAS-to-CAS Delay (RCD) bit specifies t
Setting it to "1" specifies two clock cycles; resetting it to "0," one.
DRAM Bank 2 and 3 Access Timing Control Registers (ATnCON, n=2,3)
7
0
6
0
A "0” indicates a reserved bit. Always write "0” to it.
Writing "1” produces unreliable operation.
5
0
4
0
3
0
RP
, the RAS precharge time, for bank n.
RP
2
RCD
RP
, the RAS-to-CAS delay, for bank n.
) and the RAS-to-CAS delay (t
1
0
RCD
0
0 RAS-to-CAS delay, tRCD ,
1 RAS-to-CAS delay, tRCD ,
0 RAS precharge time, tRP ,
1 RAS precharge time, tRP ,
= 1 clock cycle
= 2 clock cycles
= 1 clock cycle
= 2 clock cycles
RCD
), the
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