ml670100 Oki Semiconductor, ml670100 Datasheet - Page 194

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.5
11-38
SYSCLK
(CLKOUT)
Peripheral
address bus
nR/W
Peripheral
data bus
The bank 0 internal memory areas consist of four 2-megabyte areas assigned to internal ROM,
internal RAM, control registers on the core bus, and control registers on the peripheral bus.
Access to the first two takes one clock cycle. Access to the fourth, which links control registers
outside the CPU control unit, takes two clock cycles. Access to the third, which links CPU
control unit control registers, one clock cycle for a read and at least two clock cycles for a write.
Figure 11.33 shows the access timing for internal ROM and RAM; Figure 11.34, that for
internal I/O devices on the peripheral bus.
Accessing Bank 0 Internal Memory Areas
SYSCLK
(CLKOUT)
Core address bus
nR/W
Core data bus
Figure 11.34 : Access Timing for Internal I/O Devices on Peripheral Bus
Figure 11.33 : Internal ROM/RAM Access Timing
Read cycle
Read
Read cycle
Read
Read
Read
Write cycle
Write cycle
Write
Write
Write
Write