ml670100 Oki Semiconductor, ml670100 Datasheet - Page 195

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.4
11.4.1
11.4.2
SYSCLK
(CLKOUT)
SYSCLK
(CLKOUT)
nBREQ
nBACK
XA, XD and
Control pins
nBREQ
nBACK
XA, XD and
Control pins
The External Memory Controller (XMC) arbitrates access to the external bus by two types of
bus masters: the CPU and external devices. External devices cannot access the core and
peripheral buses inside this LSI.
The controller arbitrates bus access requests from external devices and grants them access.
External devices have higher priority than the CPU.
An external device gains access to the external bus by asserting the nBREQ signal to request
access and waiting for the controller to force the CPU to release the address bus, data bus, and
control pins, and assert the nBACK signal in acknowledgment - (1) in Figure 11.35. Table 11.5
lists the pins in high-impedance states when the CPU releases the external bus.
When the CAS-before-RAS (CBR) refresh request occurs, however, the controller negates the
nBACK signal to ask the external device to relinquish access. The external device must
immediately negate the nBREQ signal to release the bus. The pins in high-impedance states
return to their normal configurations, and the controller asserts the strobe signals (nRAS and
nCAS) for the CBR refresh - (2) in Figure 11.35.
Bus Arbitration
Bus Access and Priority
Requesting and Obtaining Bus Access
(2) CBR Refresh Request while External Device is Master of External Bus
Figure 11.35 :Timing for Bus Access Request and Bus release
(1) Making External Device Master
High-impedance state
High-impedance state
Refresh request
Start of refresh cycle
11-39