ml670100 Oki Semiconductor, ml670100 Datasheet - Page 162

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.1.3
11-6
Table 11.2 lists the control registers for the External Memory Controller (XMC).
Table 11.1 : External Memory Controller (XMC) Pins
Control Registers
Table 11.2 : External Memory Controller (XMC) Control Registers
Pin Name
Bus request
Bus acknowledgment
Data bus width selection
Internal ROM selection
Address
0x060_0700
0x060_0701
0x060_0702
0x060_0703
0x060_0704
0x060_0705
0x060_0706
0x060_0707
0x060_0708
0x060_0709
0x060_070A
0x060_070B
0x060_070C
0x060_070D
0x060_070E
0x060_070F
Name
Bus Width Control Register
Wait Input Control Register
Off Time Control Register
Programmable Wait Control Register
Bus Access Control Register
DRAM Bank 2 Control Register
DRAM Bank 2 Access Timing Control
Register
DRAM Bank 2 Programmable Wait
Control Register
DRAM Bank 3 Control Register
DRAM Bank 3 Access Timing Control
Register
DRAM Bank 3 Programmable Wait
Control Register
Refresh Timer Counter
Refresh Cycle Control Register
Refresh Timing Control Register
Refresh Control Register
Cycle Trace Control Register
Symbol
nBREQ
nBACK
DBSEL
nEA
Direction Description
Input
Output
Input
Input
This input is a bus request signal from an external device. It
represents a secondary function for I/O port PIO7[6].
This output is an acknowledgment signal to a bus request signal
from an external device. It represents a secondary function for I/O
port PIO7[7].
During a system reset of this LSI, this input specifies the width of
the external data bus for bank 0. Connect this pin to V
data bus width of 16 bits and to ground for 8 bits.
During a system reset of this LSI, this input controls the use of the
internal ROM. Connect this pin to V
ground to disable it.
Symbol
BWCON
WICON
OTCON
PWCON
BACON
DR2CON
AT2CON
DW2CON
DR3CON
AT3CON
DW3CON
RFTCN
RCCON
RTCON
RFCON
CTCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DD
Size
(bits)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
to enable the ROM and to
Initial value
0x0E/0F
0x00
0xFF
0x77
0x00
0x00
0x05
0x03
0x00
0x05
0x03
0xFF
0xFF
0x37
0x00
0x00
DD
for a