ml670100 Oki Semiconductor, ml670100 Datasheet - Page 62

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

4.4
4.4.1
4.4.1.1
4.4.2
4-14
Each external and internal interrupt source has, as shown in Table 4.3, its own
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Interrupt Processing
External Fast Interrupt Requests
If there is an external fast interrupt request and the external FIQ mask (EFIQM) flag in the
External FIQ Control Register (EFIQCON) does not mask it, the interrupt controller sends the
CPU an FIQ exception request.
Interrupt Sequence
(1)
(2)
(3)
(4)
(5)
(6)
External and Internal Interrupt Requests
Interrupt arrives.
The interrupt controller detects an external fast interrupt request from the external fast
interrupt request (nEFIQ ) pin.
Interrupt is noted.
The interrupt controller sets the EFIQR bit in the External FIQ Control Register
(EFIQCON) to "1" to indicate that an external fast interrupt request has been received.
Interrupt passes to CPU.
If the EFIQM flag in EFIQCON is not masking external fast interrupt requests, the
interrupt controller asserts the nFIQ signal to send the CPU an FIQ exception request.
CPU accepts FIQ exception.
If the CPU is accepting FIQ exception requests - that is, if the F bit in its Current
Program Status Register (CPSR) is not masking them - it switches to FIQ exception
handling, setting the F and I bits in CPSR to "1" to disable FIQ and IRQ exceptions.
Handler processes interrupt.
In addition to the usual interrupt processing, the FIQ handler writes "1" to the EFIQR bit
to clear the interrupt request flag and negate the nFIQ signal.
Handler terminates.
The handler relinquishes control by executing the appropriate return instruction.
Interrupt number
Pending flag in the Interrupt Request Registers 0 to 3 (IRRn, n=0 - 3)
Interrupt level field (ILRn, n=0 - 31) in the Interrupt Level Control Registers 0 to
15(ILCONn, n=0 - 15)
Fixed priority