ml670100 Oki Semiconductor, ml670100 Datasheet - Page 159

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.1.1
Block Diagram
Figure 11.1 gives a block diagram for the External Memory Controller (XMC), which includes
the following components:
There are two internal buses: the core bus, which connects the CPU, internal ROM, internal
RAM, and control registers for the CPU control unit, and the peripheral bus, which connects all
control registers outside the CPU control unit.
- Bus Width Control Register (BWCON), which controls the external data bus width for
- Wait Input Control Register (WICON), which controls the use of nXWAIT input to insert
- Off Time Control Register (OTCON), which controls the "off time" for each bank
- Programmable Wait Control Register (PWCON) and Bus Access Control Register
- DRAM Bank Control Registers 2,3 (DRnCON, n=2,3), DRAM Bank Access Timing
- Refresh Timer Counter (RFTCN), Refresh Cycle Control Register (RCCON), Refresh
each bank
wait cycles for each bank
(BACON), which control wait cycles and other access parameters for the SRAM banks (0
and 1)
Control Registers 2,3 (ATnCON, n=2,3), DRAM Bank Programmable Wait Control
Registers 2,3 (DWnCON, n=2,3), which control address multiplexing, wait cycles, and
other parameters for the DRAM banks (2 and 3)
Timing Control Register (RTCON), and Refresh Control Register (RFCON), which
control DRAM refresh for the DRAM banks (2 and 3)
11-3