ml670100 Oki Semiconductor, ml670100 Datasheet - Page 36

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

2.9.1
2.9.2
2.9.3
It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of
exceptions.
If the CPU is in THUMB state when an exception occurs, it will automatically switch into ARM
state when the PC is loaded with the exception vector address.
Table 2.2 : Exception entry/exit summarizes the PC value preserved in the relevant R14 on
exception entry, and the recommended instruction for exiting the exception handler.
Action on entering an exception
When handling an exception, the CPU:
Action on leaving an exception
On completion, the exception handler:
Note :
Exception entry/exit summary
1
2
3
4
1
2
3
Preserves the address of the next instruction in the appropriate Link Register. If the
exception has been entered from ARM state, then the address of the next instruction is
copied into the Link Register (that is, current PC + 4 or PC + 8 depending on the
exception. See Table 2.2 Exception entry/exit for details). If the exception has been
entered from THUMB state, then the value written into the exception has been entered
from THUMB state, then the value written into the Link Register is the current PC
offset by a value such that the program resumes from the correct place on return from
the exception. This means that the exception handler need not determine which state
the exception was entered from. For example, in the case of SWI, MOVS PC, R14_svc
will always return to the next instruction regardless of whether the SWI was executed in
ARM or THUMB state.
Copies the CPSR into the appropriate SPSR
Moves the Link Resister, minus an offset where appropriate, to the PC.(The offset will
vary depending on the type of exception.)
Copies the SPSR back to the CPSR
Clears the interrupt disable flags, if they were set on entry
Forces the CPSR mode bits to a value which depends on the exception
Forces the PC to fetch the next instruction from the relevant exception vector
An explicit switch back to THUMB state is never needed, since restoring the
CPSR from the SPSR automatically sets the T bit to the value it held immediately
prior to the exception.
2-10