ml670100 Oki Semiconductor, ml670100 Datasheet - Page 112
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ml670100
Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
1.ML670100.pdf
(204 pages)
- Current page: 112 of 204
- Download datasheet (500Kb)
7.4.2
7-20
In capture (CAP) mode, a Flexible Timer (FTM) channel configures its Timer Input/Output n
pin (TMIN[n]/TMOUT[n], n=0 - 5) as a capture trigger input pin TMIN[n] (n=0 -5) with
high-impedance input.
Figure 7.16 shows the timing with which the timer channel samples the signal from Timer
Input n pin (TMIN[n], n=0 - 5) and uses transitions over the sampling interval to derive the
load signal for copying the Timer Counter n (TMnC, n=0 - 5) contents to Timer General-
Purpose Register n (TMnGR, n=0 - 5). Sampling is always at the rising edges of the system
clock (SYSCLK) signal; copying, two SYSCLK rising edges later.
If the IOLV field in Timer I/O Level Register n (TMnIOLV, n=0 - 5) specifies rising edges as
capture triggers, a transition from "L" level to "H" level produces a load signal pulse.
If IOLV specifies falling edges, a transition from "H" level to "L" level produces a load signal
pulse. (Note that IOLV can specify both edges.)
The TMIN[n] (n=0 - 5) input signal must have "H" level and "L" level pulses that are at least
two system clock (SYSCLK) cycles long.
Capture Trigger Input Sampling
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