ml670100 Oki Semiconductor, ml670100 Datasheet - Page 187

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.3.3.4 nXWAIT Input Wait Cycles
11.3.3.4 Half Word Access
Figure 11.25 : Access Timing with Two Programmable Wait Cycles and nXWAIT Input
Bits 2 and 3 in the Wait Input Control Register (WICON) enable/disable the use of nXWAIT
input to insert additional wait cycles for each bank. Setting a bit to "1" enables sampling for the
corresponding bank, causing the controller to insert wait cycles when the nXWAIT signal is
asserted at the rising edges of the system clock (SYSCLK) signal.
This input must therefore satisfy setup and hold time conditions at these edges.
Figure 11.25 shows the access timing with two programmable wait cycles inserted and the
nXWAIT signal asserted.
Two access methods are available for 16-bit bus access to the DRAM banks (2 and 3): with one
Write Enable signal and two Column Address Strobe signals (nWE, nCASH, and nCASL) or
with two Write Enable signals and one Column Address Strobe signal (nWL, nWH, and nCAS).
The Data Byte Access Specification (DBAS) bit in the DRAM Bank 2 and 3 Control Registers
(DRnCON, n=2,3) specifies which, switching the nWE/nWL, nCASH/nWH, and
nCASL/nCAS pins between two different configurations.
Figure 11.26 shows the write access timing for both access methods.
SYSCLK
(CLKOUT)
XA15 - XA0
nRAS
nCAS
XD15 - XD0
nXWAIT
Row
Read cycle
Two cycles
Col
nXWAIT input
wait cycle
Read
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