ml670100 Oki Semiconductor, ml670100 Datasheet - Page 65

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

t4. IRQ handler processes level 2 interrupt.
t5. Level 7 interrupt arrives.
t6. CPU accepts IRQ exception.
t7. IRQ handler reads INR.
t8. IRQ handler processes level 7 interrupt.
t9. Fast interrupt request arrives.
t10. CPU accepts FIQ exception.
t11. FIQ handler clears EFIQR.
t12. FIQ handler terminates.
t13. IRQ handler clears level 7 interrupt request.
t14. IRQ handler clears CILR[7].
t15. IRQ handler terminates.
t16. IRQ handler clears level 2 interrupt request.
The IRQ handler reads the interrupt number from INR. Because IRLR contains 7, the
interrupt controller sets CILR[7] to "1" and negates the nIRQ signal.
The interrupt controller asserts the nFIQ signal to send the CPU an FIQ exception request.
Control passes to the FIQ handler.
The FIQ handler writes "1" to the EFIQR bit to clear the interrupt request flag and negate
the nFIQ signal.
The FIQ handler executes the SUBS PC,R14_fiq,#4 instruction to return control to
processing of the level 7 interrupt, interrupted by the FIQ exception.
The IRQ handler writes "1" to the pending flag corresponding to the current interrupt
source in the Interrupt Request Registers 0 to 3 (IRRn, n=0 - 3) to clear the interrupt
request.
Just before terminating level 7 interrupt processing, the IRQ handler clears CILR[7].
The IRQ handler executes the SUBS PC,R14_irq,#4 instruction to return control to
processing of the level 2 interrupt, interrupted by the level 7 interrupt.
The IRQ handler writes "1" to the pending flag corresponding to the current interrupt
source in the Interrupt Request Registers 0 to 3 (IRRn, n=0 - 3) to clear the interrupt
request.
To enable interrupt requests with higher interrupt levels, the IRQ handler saves the Link
Register (R14_irq) and the Saved Program Status Register (SPSR_irq) to the stack and
then resets the I bit in CPSR to "0."
The interrupt controller sets IRLR to 7 and asserts the nIRQ signal to send the CPU an
IRQ exception request.
Control passes to the IRQ handler.
4-17