ml670100 Oki Semiconductor, ml670100 Datasheet - Page 183

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ml670100

Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
11.3.3
11.3.3.1 Address Multiplexing
The Address Multiplexing (AMUX) field in the bank's DRAM Bank 2 and 3 Control Registers
(DRnCON, n=2,3) specifies the number of bits that the multiplexed address shifts the row
address. The range is from 8 to 11. Table 11.4 shows the effect of each setting on the address
outputs.
Accessing External Memory in DRAM Banks (2 and 3)
The external memory areas in the DRAM banks (2 and 3) are designed primarily for direct
connection to DRAM devices. Accessing them automatically generates an address signal
multiplexing the upper (row) and lower (column) addresses and the appropriate strobe signals
(nRAS and nCAS).
Table 11.4 : AMUX Setting and Row Address Outputs
XA23
XA22
XA21
XA20
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XA11
XA10
XA9
XA8
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0
Chip pin
Indeterminate
XA23
XA22
XA21
XA20
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XA11
XA10
XA9
XA8
(8-bit shift)
Indeterminate
Indeterminate
XA23
XA22
XA21
XA20
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XA11
XA10
XA9
(9-bit shift)
Indeterminate
Indeterminate
Indeterminate
XA23
XA22
XA21
XA20
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XA11
XA10
(10-bit shift)
Indeterminate
Indeterminate
Indeterminate
Indeterminate
XA23
XA22
XA21
XA20
XA19
XA18
XA17
XA16
XA15
XA14
XA13
XA12
XA11
(11-bit shift)
11-27

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