ml670100 Oki Semiconductor, ml670100 Datasheet - Page 173

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ml670100

Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
11.2.9
11.2.10
The Refresh Timer Counter (RFTCN) is an 8-bit read/write decrementing counter that controls
the timing for CAS-before-RAS (CBR) refresh cycle requests for the DRAM banks (2 and 3). It
uses a time base clock from the Time Base Generator (TBG) as its count clock and the contents
of the Refresh Cycle Control Register (RCCON) as its starting value. Setting either CBRR bit
in the Refresh Control Register (RFCON) to "1" loads this register from RCCON and starts the
countdown. When the count reaches 0x00, the circuitry initiates a CBR refresh cycle, waits for
it to complete, reloads this register from RCCON, and starts a new countdown.
The Refresh Cycle Control Register (RCCON) is an 8-bit read/write register holding a starting
value that determines the interval between CAS-before-RAS (CBR) refresh cycles for the
DRAM banks (2 and 3). Setting either CBRR bit in the Refresh Control Register (RFCON) to
"1" loads the contents of this register into the Refresh Timer Counter (RFTCN) and starts the
countdown. When the count reaches 0x00, the circuitry initiates a CBR refresh cycle, waits for
it to complete, reloads the contents of this register into RFTCN, and starts a new countdown.
After a system reset, this register contains 0xFF.
After a system reset, this register contains 0xFF.
Refresh Cycle Control Register (RCCON)
Refresh Timer Counter (RFTCN)
Figure 11.12 : Refresh Cycle Control Register (RCCON)
Figure 11.11 : Refresh Timer Counter (RFTCN)
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