ml670100 Oki Semiconductor, ml670100 Datasheet - Page 143

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

9.4.2
SYSCLK
(CLKOUT)
CSIn_SCLK
CSIn_TXD
CSIn_RXD
Figure 9.8 gives the I/O signal timing for slave mode. The serial port samples the
synchronization clock signal from the CSIn_SCLK (n=0,1) pin, shifts the transmit data to the
CSIn_TXD (n=0,1) pin, and samples the incoming data at the CSIn_RXD (n=0,1) pin. It
samples the two inputs at the rising edges of the system clock (SYSCLK) signal. It shifts and
transmits outgoing bits at transitions from "H" level to "L" level in the sampled
synchronization clock signal. The sampled incoming data becomes valid at transitions from "L"
level to "H" level in that signal.
In slave mode, the synchronization clock signal from the CSIn_SCLK (n=0,1) pin must have a
period at least four times that of the system clock (SYSCLK) period.
Slave Mode I/O Signal Timing
Figure 9.8 : Slave Mode I/O Signal Timing
Sampling
9-11