ml670100 Oki Semiconductor, ml670100 Datasheet - Page 68

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

4.5
4-20
The interrupt controller samples the external fast interrupt request signal from the nEFIQ pin
and the external interrupt request signals from the nEIR[7:0] pins and sets the corresponding
interrupt request bits to "1" when it detects input.
Figure 4.10 shows the timing with which the interrupt controller samples the external fast
interrupt request signal from the nEFIQ pin and sets the EFIQR bit in the External FIQ Control
Register (EFIQCON) to "1."
The interrupt controller samples the nEFIQ input at the rising edges of the system clock
(SYSCLK) signal. A transition from "H" level to "L" level over the sampling interval causes
the interrupt controller, at the next SYSCLK rising edge, to set the EFIQR bit to "1" and send
the CPU an FIQ exception request.
The nEFIQ input signal must have "H" level and "L" level pulses that are at least two system
clock (SYSCLK) cycles long.
Figure 4.11 shows the timing with which the interrupt controller samples the external interrupt
request signal from External Interrupt n pin (nEIR[n] , n=0 - 7) and sets the corresponding
pending flag in Interrupt Request Register 3 (IRR3) to "1."
The interrupt controller samples the nEIR[n] input at the rising edges of the system clock
(SYSCLK) signal. If the corresponding bit in the External IRQ Control Register (EIRCON)
specifies falling edge sensing for interrupt request detection, a transition from "H" level to "L"
level over the sampling interval causes the interrupt controller to set the corresponding pending
flag in IRR3 to "1" at the next SYSCLK rising edge and send the CPU an IRQ exception
request.
If that bit specifies "L" level sensing, "L" level input causes the interrupt controller to set the
corresponding pending flag in IRR3 to "1" at the next SYSCLK rising edge and send the CPU
an IRQ exception request. The interrupt controller continues setting that bit as long as
sampling detects "L" level input.
The nEIR[n] (n=0 - 7) input signal must have "H" level and "L" level pulses that are at least
two system clock (SYSCLK) cycles long.
Sampling Timing for External Interrupt Requests
SYSCLK
(CLKOUT)
nEFIQ pin
EFIQR bit
Figure 4.10 : Sampling Timing for External Fast Interrupt Requests
Set