ml670100 Oki Semiconductor, ml670100 Datasheet - Page 64

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

4.4.2.3
4-16
Figure 4.9 gives an example of a level 7 interrupt interrupting processing of a level 2 interrupt
and then itself being interrupted by an FIQ exception.
t1. Level 2 interrupt arrives.
t2. CPU accepts IRQ exception.
t3. IRQ handler reads INR.
(4)
(5)
(6)
(7)
Example of Interrupt Level Control
The interrupt controller sets the Interrupt Request Level Register (IRLR) to 2 and asserts
the nIRQ signal to send the CPU an IRQ exception request.
Control passes to the IRQ handler.
The IRQ handler reads the interrupt number from the interrupt controller's Interrupt
Number Register (INR). In response to this read, the interrupt controller sets bit 2 in the
Current Interrupt Level Register (CILR[2]) to "1" and negates the nIRQ signal.
CPU accepts IRQ exception.
If the CPU is accepting IRQ exception requests - that is, if the I bit in its Current Program
Status Register (CPSR) is not masking them - it switches to IRQ exception handling,
setting the I bit in CPSR to "1" to disable IRQ exceptions.
Handler distinguishes between interrupts.
The IRQ handler reads the interrupt number from the interrupt controller's Interrupt
Number Register (INR). In response to this read, the interrupt controller sets the CILR bit
corresponding to the interrupt level assigned to that interrupt source and negates the
nIRQ signal.
Handler processes interrupt.
In addition to the usual interrupt processing, the IRQ handler
• Enables IRQ exceptions.
• Clears the interrupt request.
Handler terminates.
The handler resets the CILR bit corresponding to the interrupt level assigned to the
interrupt source to "0" and then relinquishes control by executing the appropriate return
instruction.
To allow interrupt requests with higher interrupt levels to interrupt it, the handler
saves the Link Register (R14_irq) and the Saved Program Status Register (SPSR_irq)
to the stack and then resets the I bit in CPSR to "0" to enable IRQ exceptions.
The handler writes "1" to the corresponding pending flag in the Interrupt Request
Registers 0 to 3 (IRRn, n=0 - 3) to clear the interrupt request.