ml670100 Oki Semiconductor, ml670100 Datasheet - Page 170

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.2.6
11-14
controls access to DRAM bank n, specifying the row address shift for the multiplexed address,
the access method (two Column Address Strobe signals or two Write Enable signals) for 16-bit
access, and the access mode (random access or high-speed paged).
Bit Descriptions
AMUX
The Address Multiplexing (AMUX) field specifies the number of bits that the multiplexed
address for bank n shifts the row address. Select the number, between 8 and 11, that matches
the DRAM and the data bus width.
DBAS
The Data Byte Access Specification (DBAS) bit specifies the access method for 16-bit access to
bank n, switching the nWL/nWE , nWH/nCASH, and nCAS/nCASL pins between two
different configurations. Setting it to "1" configures the pins as two Write Enable signals and
one Column Address Strobe signal (nWL, nWH, and nCAS); resetting it to "0," as one Write
Enable signal and two Column Address Strobe signals (nWE, nCASH, and nCASL).
DRAM Bank 2 and 3 Control Registers (DRnCON, n=2,3)
The DRAM Bank n Control Register (DRnCON, n=2,3) is an 8-bit read/write register that
After a system reset, this register contains 0x00.
7
0
Figure 11.8 : DRAM Bank 2 and 3 Control Registers (DRnCON, n=2,3)
6
0
A "0” indicates a reserved bit. Always write "0” to it.
Writing "1” produces unreliable operation.
5
0
4
0
3
AMUX
2
DBAS
1
BE
0
0
1
0
1
00
01
10
11
Random access mode
High-speed paged mode
Access bank with two CAS
signals
Access bank with two WE
signals
Row address shift = 8 bits
Row address shift = 9 bits
Row address shift = 10 bits
Row address shift = 11 bits