ml670100 Oki Semiconductor, ml670100 Datasheet - Page 140

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

9.3
9-8
Write to CSInSFT
(signal to enable
BUSY bit in CSInST
CSIn_SCLK
CSIn_TXD
CSIn_RXD
Transfer complete
interrupt request n
(CSINTn)
transfer)
CSI Shift Register n (CSInSFT, n=0,1) is an 8-bit shift register that simultaneously shifts bits
in from the CSIn_RXD (n=0,1) pin and shifts bits out from the CSIn_TXD (n=0,1) pin using
the synchronization clock signal at the CSIn_SCLK (n=0,1) pin. These transfers are LSB first.
When the transfer is complete, the serial port generates a transfer complete interrupt request n
(CSINTn, n=0,1).
Figure 9.6 gives the timing for the entire transfer.
Clock Synchronous Serial Interface (CSI) Operation
The serial port can be master or slave. In master mode, it uses a synchronization clock signal
generated internally to shift the incoming and outgoing data and feeds that clock signal to the
CSIn_SCLK (n=0,1) pin. In slave mode, it takes the synchronization clock from an external
source via the CSIn_SCLK (n=0,1) pin.
The serial port writes an outgoing bit to the CSIn_TXD (n=0,1) pin at the falling edge of the
CSIn_SCLK (n=0,1) signal and reads an incoming one at the rising edge. In other words, this
LSI assumes that external devices transmit at the rising edge and receive at the falling edge of
the synchronization clock signal.
Enabling a transfer requires writing data to the CSI Shift Register (CSInSFT, n=0,1). If the
program is only receiving, it still must write dummy data. This write sets the BUSY bit in CSI
Status Register n (CSInST, n=0,1) to "1." When the 8-bit transfer is complete, the serial port
automatically resets this flag to "0" and generates a transfer complete interrupt request n
(CSINTn, n=0,1).
Figure 9.6 : Clock Synchronous Serial Interface Operation Timing
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7