ml670100 Oki Semiconductor, ml670100 Datasheet - Page 161

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.1.2
Pins
Table 11.1 lists the pins connected to the External Memory Controller (XMC).
Table 11.1 : External Memory Controller (XMC) Pins
Pin Name
External address
bus
External data bus
Bank 0 chip select
Bank 1 chip select
SRAM bank (0 or 1) read
SRAM bank (0 or 1) write nWRE/nWRL Output
SRAM bank (0 or 1) write nHB/nWRH
Bank 2 RAS
Bank 3 RAS
DRAM bank (2 or 3) CAS nCASL/nCAS Output
DRAM bank (2 or 3)
write/CAS
DRAM bank (2 or 3) write nWE/nWL
Wait input
Symbol
XA23-XA1,
nLB/XA0
XD15-XD0
nCS0
nCS1
nRD
nRAS0
nRAS1
nCASH/nWH Output
nXWAIT
Direction
Output
Bi-directional These are the external data bus. The upper eight bits, XD15
Output
Output
Output
Output
Output
Output
Output
Input
Description
These outputs are the external address bus. The least
significant bit, nLB/XA0, doubles as bit 0 of the external
address bus and as the Low Byte Select signal for the SRAM
banks (0 and 1). The top eight bits, XA23 to XA16,
represent secondary functions
for I/O port PIO0[7:0].
to XD8, represent secondary functions for I/O port
PIO1[7:0].
This output is the chip select signal for bank 0.
This output is the chip select signal for bank 1. It represents
a secondary function for I/O port PIO2[6].
This output is the read signal for the SRAM banks (0 and 1).
This output is the Write Enable Low signal (nWRL) or
Write Enable signal (nWRE) for the SRAM banks (0 and 1).
This output is the Write Enable High signal (nWRH) or
High Byte Select signal (nHB) for the SRAM banks (0 and
1). It represents a secondary function for I/O port PIO2[5].
This output is the Row Address Strobe signal for bank 2. It
represents a secondary function for I/O port PIO2[2].
This output is the Row Address Strobe signal for bank 3. It
represents a secondary function for I/O port PIO2[4].
This output is the Column Address Strobe signal (nCAS) or
Column Address Strobe Low signal (nCASL) for the DRAM
banks (2 and 3). It represents a secondary function for I/O
port PIO2[1].
This output is the Write Enable High signal (nWH) or
Column Address Strobe High signal (nCASH) for the
DRAM banks (2 and 3). It represents a secondary function
for I/O port PIO2[3].
This output is the Write Enable Low signal (nWL) or Write
Enable signal (nWE) for the DRAM banks (2 and 3). It
represents a secondary function for I/O port PIO2[0].
This input pin controls insertion of wait cycles. It represents
a secondary function for I/O port PIO2[7].
11-5