ml670100 Oki Semiconductor, ml670100 Datasheet - Page 189

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.3.6 Refresh Access
11.3.3.6.1 CAS-before-RAS (CBR) Refresh Function
RCCON
RFTCN value
The External Memory Controller (XMC) offers two types of DRAM refresh functions: a CAS-
before-RAS (CBR) refresh function and two self-refresh functions.
Setting either CBRR bit in the Refresh Control Register (RFCON) to "1" activates the CAS-
before-RAS (CBR) refresh function. The lower and upper bits in this field control the function
for the DRAM banks (2 and 3), respectively. Setting both bits to "1" refreshes bank 2 and then
bank 3.
Two parameters determine the refresh interval: the count clock, specified by the Clock
Selection (CLKS) field in RFCON, and the counter value in the Refresh Cycle Control Register
(RCCON). The program must therefore set these to produce an interval matching the DRAM
CBR refresh specifications.
Setting CBRR to a nonzero value (2’b01, 2'b10, or 2'b11) loads the contents of RCCON into the
Refresh Timer Counter (RFTCN) and starts the countdown. When the count reaches 0x00, the
circuitry initiates a CAS-before-RAS (CBR) refresh cycle, reloads RFTCON from RCCON, and
starts a new countdown. Do not change the CBRR field after replacing the initial 00b with a
nonzero value to activate the CAS-before-RAS (CBR) refresh function. Changing from a
nonzero value to any other value produces unreliable operation.
Figure 11.28 shows Refresh Timer Counter operation and CBR refresh cycles; Figure 11.29,
CBR refresh timing.
Figure 11.28 : Refresh Timer Counter Operation and CBR Refresh Cycles
0x00
CBR refresh
cycle
CBR refresh
cycle
CBR refresh
cycle
CBR refresh
cycle
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