ml670100 Oki Semiconductor, ml670100 Datasheet - Page 176

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

Bit Descriptions
CLKS
The Clock Selection (CLKS) field specifies the count clock for the Refresh Timer Counter
(RFTCN). The choices are the time base clocks 2TBCCLK to 256TBCCLK.
RSR
The Self-Refresh (RSR) bit switches to and from DRAM self-refresh operation.
Setting this bit to "1" causes completion of the current access to assert first the nCAS signal and
then the nRAS signal long enough to activate DRAM self-refresh operation. Subsequent access
to a DRAM bank (2 or 3) resets this bit to "0" and automatically switches back from self-refresh
mode to normal operation mode. Writing "0" to this bit forces a return as well. When switching
back from self-refresh mode, the controller negates the nRAS signal, first waits the number of
clock cycles specified by the CAS Hold Self-refresh (CHS) field in the Refresh Timing Control
Register (RTCON) before negating the nCAS signal, and then waits the number of clock cycles
specified by the RAS Precharge Self-refresh (RPS) field in RTCON before asserting the nRAS
signal to disable DRAM self-refresh operation and switch back to normal operation mode.
CBRR
Bits 0 and 1 control CAS-before-RAS (CBR) refresh for the DRAM banks (2 and 3),
respectively.
Do not change this field more than once. Changing the initial 00b to a nonzero value and then
to any other value produces unreliable operation.
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