ml670100 Oki Semiconductor, ml670100 Datasheet - Page 179

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.1
Bus Width Bit n (BWBn, n=0 - 3) in the Bus Width Control Register (BWCON) specifies
whether the external bus for bank n is 8 or 16 bits wide. Note, however, that access to the
internal ROM, internal RAM, and I/O devices on the core bus - that is, control registers for the
CPU control unit - is always 32 bits wide; to internal I/O devices on the peripheral bus - that is,
control registers outside the CPU control unit - 16 bits wide.
After a system reset, the BWB0 bit reflects the DBSEL input level during the reset. "H" level (V
DD
bits. This initial setting can be changed by modifying BWCON.
Half word (16-bit) access over an 8-bit bus or word (32-bit) access over a 16-bit bus takes two
successive bus cycles; word (32-bit) access over an 8-bit bus, four.
Bank 1 is for external devices (ROM, RAM, or I/O devices).
Banks 2 and 3 are for DRAM. Accessing an address in these ranges generates the appropriate
nRAS, nCAS, and multiplexed address signals.
External memory areas offer a separate data bus width (8 or 16) specification for each bank.
Data Bus Width
Note : Do not access addresses between 0x00000000 and 0x006FFFFF for which there is
- Addresses 0x00700000 to 0x007FFFFF are a reserved area and must not be used.
- Addresses 0x00800000 to 0x008FFFFF are for external devices (ROM, RAM, or I/O
) input (BWB0 = "1") sets the width to 16 bits; "L" level (GND) input (BWB0 = "0"), to 8
devices).
no internal ROM, internal RAM, or control register physically present or addresses
0x00700000 to 0x007FFFFF. Doing so produces unreliable operation.
11-23