ml670100 Oki Semiconductor, ml670100 Datasheet - Page 102

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

7.2.6
7-10
Timer I/O Level Register n (TMnIOLV, n=0 - 5) is an 8-bit read/write register that, in the
compare out (CMO) and pulse width modulation (PWM) modes, specifies the output level for
Timer Output n pin (TMOUT[n], n=0 - 5) and, in capture (CAP) mode, specifies the trigger
condition for capture event input from Timer Input n pin (TMIN[n], n=0 - 5).
After a system reset, this register contains 0x00.
Timer I/O Level Registers 0 to 5 (TMnIOLV, n=0 - 5)
7
0
Figure 7.7 : Timer I/O Level Registers 0 to 5 (TMnIOLV, n=0-5)
6
0
5
0
A "0" indicates a reserved bit. Always write "0" to it.
Writing "1" produces unreliable operation.
4
0
3
0
2
0
1
IOLV
0
Compare out (CMO)mode
Pulse width modulation(PWM) mode
Capture (CAP)mode
IOLV
00
01
10
11
IOLV
00
01
1X
IOLV
00
01
10
11
Timer output
Set to "0” if TMnC matches TMnGR.
Set to "1” if TMnC matches TMnGR.
Reverse if TMnC matches TMnGR.
Operation not guaranteed.
Timer output
Set to "0" if TMnC is equal to or less
than TMnGR, and to "1” otherwise.
Set to "1” if TMnC is equal to or less
than TMnGR, and to "0” otherwise.
Operation not guaranteed.
Event trigger
Ignore events.
Rising edges of TMIN[n]
Falling edges of TMIN[n]
Both edges of TMIN[n]