ml670100 Oki Semiconductor, ml670100 Datasheet - Page 108
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ml670100
Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
1.ML670100.pdf
(204 pages)
- Current page: 108 of 204
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7.3.4
7-16
TMOUT [n]output for IOLV=
2'b00 and initial setting of "1"
TMOUT [n]output for IOLV=
2'b01 and initial setting of "0"
TMOUT [n]output for IOLV=
2'b10 and initial setting of "0"
Setting the MOD field in Timer Control Register n (TMnCON, n=0 to 5) to 2’b10 (PWM)
configures timer channel n in pulse width modulation (PWM) mode.
This mode takes the period from the Timer Register n (TMnR, n=0 - 5) and the length of the
front portion of the pulse from the Timer General-Purpose Register n (TMnGR, n=0 The timer
channel sets the output level for Timer Output n pin (TMOUT[n], n=0 - 5) according to the
IOLV field in Timer I/O Level Register n (TMnIOLV, n=0 - 5).
2’b00: Set output level to "0" if TMnC is equal to or less than TMnGR and to "1" otherwise.
2’b01: Set output level to "1" if TMnC is equal to or less than TMnGR and to "0" otherwise.
Counter overflow generates an interrupt request (FTMOVn, n=0 - 5).
Figure 7.13 illustrates pulse width modulation (PWM) operation.
Pulse Width Modulation (PWM) Mode
TMnGR value
Starting value
(from TMnR)
EVENTn
0xFFFF
0x0000
FTMOVn
TMnC contents
Figure 7.12 : Compare Out (CMO) Operation
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