ml670100 Oki Semiconductor, ml670100 Datasheet - Page 19

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

Table 1.1 : Pin Functions
Type
I/O ports
Clock
control
System
control
Signal Name Pin
PIO8[7:0]
PIO7[7:0]
PIO6[7:0]
PIO5[7:0]
PIO4[7:0]
PIO3[7:0]
PIO2[7:0]
PIO1[7:0]
PIO0[7:0]
OSC0
OSC1
CLKOUT
FSEL
PLLEN
VCOM
nRST
DBSEL
nEA
Number
36-29
28-24
21-19
18-11
130-123
120-113
111-104
101-94
88-81
66-59
133
134
131
137
138
136
139
10
68
I/O Direction Description
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Bi-directional
Input
Output
Output
Input
Input
Input
Input
Input
Input
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
These form an 8-bit I/O port. I/O directions are specified at
the bit level.
This pin is for connecting a crystal oscillator. If an external
clock is used, supply it to this pin.
This pin is for connecting a crystal oscillator. If an external
clock is used, leave this pin open.
This output is the internal system clock (SYSCLK) signal.
Connect this pin to V
range for the basic clock.
Connecting this pin to V
loop. If the PLL is not used because an external clock with a
guaranteed duty is available, connect this pin to ground.
This input controls the oscillation frequency of the PLL's
voltage-controlled oscillator. Connect it to ground.
"L" level input to this pin produces an external system reset
for this LSI. "H" level input then causes execution to resume
from address 0x000000.
During a system reset of this LSI, this input specifies the
width of the external data bus for bank 0. Connect this pin to
V
During a system reset of this LSI, this input controls the use
of the internal ROM. Connect this pin to V
ROM and to ground to disable it..
DD
for a data bus width of 16 bits and to ground for 8 bits.
DD
or ground to indicate the frequency
DD
enables the built-in phase-locked
DD
to enable the
1-9