ml670100 Oki Semiconductor, ml670100 Datasheet - Page 44

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

3.2.2
3-4
(1) a preceding interrupt request has set a bit in the Interrupt Request Registers 0 to 3 (IRRn,
(2) a preceding external fast interrupt request (FIQ) has set the EFIQR bit in the External FIQ
(3) I/O port 8 is configured for its secondary function, and DBGRQ (PIO8[1]) is asserted.
In the first case, either clear the bit in the Interrupt Request Register (IRRn) or set the interrupt
level to zero and then write to SBYCON.
The Clock Control Register (CKCON) is a 32-bit read/write register controlling the frequency
divider ratio for the system clock (SYSCLK) signal for the CPU and on-chip peripherals. After
a system reset, it contains 0x00000000.
CKM
This field specifies a frequency divider ratio. The choices are 1, 1/2, and 1/4. The LSI applies
this ratio to the PLL output to derive the system clock (SYSCLK) signal for the CPU and on-
chip peripherals.
The LSI ignores the above transition requests when
In the second case, either clear the EFIQR bit to "0" or mask external fast interrupt requests by
setting the EFIQM bit to "1" and then write to SBYCON.
In the third case, wait for the external device to negate DBGRQ, terminating debugging, and
then write to SBYCON.
Clock Control Register (CKCON)
Bit Descriptions
31
0
n=0 - 3) to "1" and the corresponding interrupt level for the interrupt in the Interrupt Level
Control Registers 0 to 15 (ILCONn, n=0 - 15) is nonzero - that is, 1 to 7.
Control Register (EFIQCON) to "1" and the EFIQM bit in the same register does not mask
such requests - that is, is "0".
30
0
-- -
A "0" indicates a reserved bit. Always write "0" to it.
Writing "1" produces unreliable operation.
Figure 3.2 : Clock Control Register (CKCON)
0
3
2
0
1
CKM
0
00
01
0X
Frequency 1/4 that of PLL output
Frequency 1/2 that of PLL output
Frequency 1/1 that of PLL output
X: don't care