ml670100 Oki Semiconductor, ml670100 Datasheet - Page 35

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

2.9
Exceptions arise whenever the normal flow of a program has to be halted temporarily, for
example to service an interrupt from a peripheral. Before an exception can be handled, the
current CPU state must be preserved so that the original program can resume when the handler
routine has finished.
It is possible for several exceptions to arise at the same time. If this happens, they are dealt with
in a fixed order -see 2.9.9 Exception priorities.
Table 2.1 : PSR mode bit values
Exceptions
The mode bits
Reserved bits
M[4:0]
10000
10001
10010
10011
11011
11111
Supervisor
Undefined
System
Mode
User
IRQ
FIQ
The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits.
These determine the CPU's operating mode, as shown in Table 2.1
PSR mode bit values. Not all combinations of the mode bits define a
valid CPU mode. Only those explicitly described shall be used. The
user should be aware that if any illegal value is programmed into the
mode bits, M [4:0], then the CPU will enter an unrecoverable state.
If this occurs, reset should be applied.
The remaining bits in the PSRs are reserved. When changing a
PSR's flag or control bits, you must ensure that these unused bits are
not altered. Also, your program should not rely on them containing
specific values, since in future CPUs they may read as one or zero.
Visible THUMB state registers
R7..R0,
LR, SP
PC, CPSR
R7..R0,
LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq
R7..R0,
LR_irq, SP_irq
PC, CPSR, SPSR_irq
R7..R0,
LR_svc, SP_svc,
PC, CPSR, SPSR_svc
R7..R0
LR_und, SP_und,
PC, CPSR, SPSR_und
R7..R0,
LR, SP
PC, CPSR
R14..R0,
PC, CPSR
R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq
R12..R0,
R14_irq..R13_irq,
PC, CPSR, SPSR_irq
R12..R0,
R14_svc..R13_svc,
PC, CPSR, SPSR_svc
R12..R0,
R14_und..R13_und,
PC, CPSR
R14..R0,
PC, CPSR
Visible ARM state registers
2-9