ml670100 Oki Semiconductor, ml670100 Datasheet - Page 188

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ml670100

Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
11.3.3.5 High-Speed Paged Mode (Burst) Access
11-32
nCAS
XD15 - XD0
SYSCLK
(CLKOUT)
XA15 - XA1
nRAS
nCASH
nCASL
nWE
nWH
nWL
The Burst Enable (BE) bit in the DRAM Bank 2 and 3 Control Registers (DRnCON, n=2,3)
switches DRAM that supports high-speed paged mode from random access mode to burst
operation. Setting it to "1" enables high-speed paged mode access when the upper portion of the
address (row address) matches the row address for the preceding access.
Figure 11.27 illustrates high-speed paged mode (burst) operation.
SYSCLK
(CLKOUT)
XA15 - XA0
nRAS
nCAS
XD15 - XD0
Figure 11.26 : Half Word Write Access Timing for DRAM Banks (2 and 3)
Figure 11.27 : High-Speed Paged Mode (Burst) Access Timing
Upper byte
Row
Row
Write
Col
Read cycle
Col
Read
Read cycle Read cycle Read cycle
Col+1
Read
Col+2 Col+3
Lower byte
Row
Read
Write
Col
Read
Two Column Address
Strobe signals
Two Write Enable
signals

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