R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1011

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI has an on-chip RAM module that achieves high-speed access and can store instructions
or data.
On-chip RAM operation and write access to the RAM can be enabled or disabled through the
RAM enable bits and RAM write enable bits.
24.1
• Pages
• Memory map
Table 24.1 On-Chip RAM Address Spaces
• Ports
• Priority
Page
Page 0
Page 1
Two pages (pages 0 and 1) are provided.
The on-chip RAM is located in the address spaces shown in table 24.1.
Each page has two independent read and write ports and is connected to the internal bus (I
bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F
bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the I bus is used for access by the
DMAC via the internal DMA write bus/internal DMA read bus and bus bridge.
When requests for access to the same page from different buses coincide, the access is
processed in priority order. The priority is I bus > M bus > F bus.
Features
Section 24 On-Chip RAM
Address
H'FFF80000 to H'FFF83FFF
H'FFF84000 to H'FFF87FFF
Rev. 2.00 Sep. 07, 2007 Page 983 of 1164
Section 24 On-Chip RAM
REJ09B0321-0200