R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 269

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Note: * RD assert wait operation during the second and subsequent bus accesses differs depending on the page read
access mode setting value.
Ts
CS assert wait
RD assert wait
Tw1
Read cycle wait
Figure 9.4 Basic Bus Timing (Page Read Operation)
Bus access
A0
(first time)
Twn
Tend
(Trd)
RD assert wait*
Tn1 Tn2
and subsequent times)
Page read cycle wait
Bus access (second
A1
Twn
Tend
(Trd)
Rev. 2.00 Sep. 07, 2007 Page 241 of 1164
Tn1 Tn2
CS delay cycle during
Section 9 Bus State Controller (BSC)
cycle during read
read (end only)
CS delay
Tnm
REJ09B0321-0200
Start enable point
of next bus access