R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 785

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

17.4.7
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 17.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
Noise Filter
D
Sampling clock
Peripheral clock
Latch
C
cycle
Figure 17.17 Block Diagram of Noise Filter
Q
D
Latch
C
Q
D
Latch
C
NF2CYC
Q
Rev. 2.00 Sep. 07, 2007 Page 757 of 1164
Section 17 I
detector
detector
Match
Match
2
C Bus Interface 3 (IIC3)
1
0
REJ09B0321-0200
Internal
SCL or SDA
signal