R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 766

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
17.3.5
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
ICSR is initialized to H'00 by a power-on reset or deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 738 of 1164
REJ09B0321-0200
Bit
7
6
I
2
Bit Name
TDRE
TEND
2
C Bus Status Register (ICSR)
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
0
R/W:
Bit:
TDRE TEND RDRF NACKF STOP AL/OVE AAS
R/W
7
0
R/W
R/W
R/W
R/W
6
0
Description
Transmit Data Register Empty
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
•
Transmit End
[Clearing conditions]
•
•
[Setting conditions]
•
•
R/W
5
0
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When the start condition (including retransmission)
is issued
When slave mode is changed from receive mode to
transmit mode
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT
When the ninth clock of SCL rises with the I
format while the TDRE flag is 1
When the final bit of transmit frame is sent with the
clocked synchronous serial format
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
ADZ
0
0
2
C bus