R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 316

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
10.1.1
SYCBEEN clears the bus monitor status register and controls the detection function.
Note: When a bus access is performed with the detection function disabled (TOEN = 0), the bus
Rev. 2.00 Sep. 07, 2007 Page 288 of 1164
REJ09B0321-0200
Bit
31
30 to 19 
18
17
16 to 0
Initial value:
Initial value:
R/W:
R/W:
may freeze.
Bit:
Bit:
Bus Monitor Enable Register (SYCBEEN)
Bit Name
STSCLR
TOEN
IGAEN

R/W
STS
CLR
31
15
—
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
R
R
0
0
Initial
Value
0
All 0
0
0
All 0
28
12
—
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R/W
R/W
R
R/W
26
10
—
—
R
R
0
0
Description
Status Clear
Writing 1 to this bit clears the bus monitor status
register. Writing 0 or reading data has no effect.
0: Invalid
1: Bus monitor status register cleared
Reserved
These bits are always read as 0. The write value
should always be 0.
Timeout Detection Enable
This bit enables or disables the function that detects a
bus timeout on each bus.
0: Bus timeout detection function disabled
1: Bus timeout detection function enabled
Illegal Address Access Detection Enable
This bit enables or disables the function that detects an
illegal address access on each bus.
0: Illegal address access detection function disabled
1: Illegal address access detection function enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
TOEN IGAEN
R/W
18
—
R
0
2
0
R/W
17
—
R
0
1
0
16
—
—
R
R
0
0
0