R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 450

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.8
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Rev. 2.00 Sep. 07, 2007 Page 422 of 1164
REJ09B0321-0200
Bit
0
Bit
7 to 4
3
Bit Name
TTSA
Bit Name
—
I2BE
Timer Input Capture Control Register (TICCR)
Initial value:
Initial
Value
0
Initial
Value
All 0
0
R/W:
Bit:
—
R/W
R/W
R/W
R
R/W
R
7
0
—
R
6
0
Description
Timing Select A
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation.
Do not set this bit to 1 when the channel is to be used
in a mode other than PWM mode.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
1: Includes the TIOC2B pin in the TGRB_1 input
—
R
5
0
capture conditions
input capture conditions
—
R
4
0
I2BE I2AE I1BE I1AE
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0