R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 13

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4
7.5
Section 8 Cache .................................................................................................183
8.1
8.2
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................201
9.1
9.2
9.3
9.4
7.3.4
7.3.5
7.3.6
Operation ........................................................................................................................... 173
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Usage Notes ....................................................................................................................... 180
Features.............................................................................................................................. 183
8.1.1
Register Descriptions ......................................................................................................... 186
8.2.1
8.2.2
Operation ........................................................................................................................... 191
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory-Mapped Cache .................................................................................................... 196
8.4.1
8.4.2
8.4.3
8.4.4
Features.............................................................................................................................. 201
Input/Output Pins ............................................................................................................... 203
Area Overview ................................................................................................................... 205
9.3.1
9.3.2
Register Descriptions ......................................................................................................... 207
9.4.1
9.4.2
9.4.3
Break Data Mask Register (BDMR)..................................................................... 167
Break Bus Cycle Register (BBR).......................................................................... 168
Break Control Register (BRCR) ........................................................................... 170
Flow of the User Break Operation ........................................................................ 173
Break on Instruction Fetch Cycle.......................................................................... 174
Break on Data Access Cycle................................................................................. 175
Value of Saved Program Counter ......................................................................... 176
Usage Examples.................................................................................................... 177
Cache Structure..................................................................................................... 183
Cache Control Register 1 (CCR1) ........................................................................ 186
Cache Control Register 2 (CCR2) ........................................................................ 188
Searching Cache ................................................................................................... 191
Read Access.......................................................................................................... 193
Prefetch Operation (Only for Operand Cache) ..................................................... 193
Write Operation (Only for Operand Cache).......................................................... 193
Write-Back Buffer (Only for Operand Cache)...................................................... 194
Coherency of Cache and External Memory .......................................................... 196
Address Array ....................................................................................................... 196
Data Array ............................................................................................................ 197
Usage Examples.................................................................................................... 199
Notes ..................................................................................................................... 200
Address Map ......................................................................................................... 205
Data Bus Width and Pin Function Setting for Individual Areas ........................... 206
CSn Control Register (CSnCNT) (n = 0 to 6)....................................................... 209
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ............................. 211
SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 213
Rev. 2.00 Sep. 07, 2007 Page xiii of xxviii