R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 792

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
(1) Normal case
Synchronous
clock*
SCL pin
Internally
monitored SCL
(2) When SCL is driven low at first by the slave device
Synchronous
clock*
SCL pin
Internally
monitored SCL
(3) When the rising speed of SCL is slow
Synchronous
clock*
SCL pin
Internally
monitored SCL
Rev. 2.00 Sep. 07, 2007 Page 764 of 1164
REJ09B0321-0200
1
1
1
Notes: 1. Clock whose transfer rate is set by bits CKS[3:0] in I
2. 3 to 4 t
2
C Bus Interface 3 (IIC3)
Internal delay*
pcyc
Internal delay*
Time for
monitoring SCL
Time for
monitoring SCL
Time for
monitoring SCL
Slave low
level output
when the NF2CYC bit in NF2CYC is 0 and 4 to 5 t
V
IH
Internal delay*
Monitored value is high level
2
Figure 17.22 Bit Synchronous Circuit Timing
V
V
Monitored value
is low level
IH
IH
2
Monitored value
is low level
SCL not driven to low level
SCL not driven
to low level
2
Time for
monitoring SCL
Monitored value
is high level
2
C bus control register 1 (ICCR1).
pcyc
when the NF2CYC bit is 1.
Time for
monitoring SCL
V
IH
Internal delay*
Monitored value
is high level
2
The rate is slower
than the settings.